Intel Stratix 10 E-Tile Transceiver PHY User Guide
发布时间：2018/3/17
Stratix 10 E-Tile Transceiver PHY Overview
Intel? Stratix? 10 devices offer up to 144 transceivers with integrated high-speed analog signal conditioning and clock data recovery circuits for chip-to-chip, chip-to-module, and backplane applications.
Intel? Stratix? 10 devices contain a combination of GX, GXT, or GXE channels in addition to hardened IP blocks for PCI Express and Ethernet applications.
Intel? Stratix? 10 devices introduce several transceiver tile variants to support a wide variety of protocol implementations. These transceiver tile variants are L-, H-, and E-Tiles. This user guide focuses on E-Tile transceivers.
| Tile | Channel Type | Channel Capability | Channel Hard IP access | |
|---|---|---|---|---|
| Chip-to-Chip | Backplane | |||
| L-Tile | GX | 17.4 Gbps (Non-Return-to-Zero (NRZ)) | 12.5 Gbps (NRZ) | PCIe Gen3x16 |
| GXT | 26.6 Gbps | |||
| H-Tile | GX | 17.4 Gbps (NRZ) | 17.4 Gbps (NRZ) | PCIe Gen3x16 50G/100G Ethernet MAC |
| GXT | 28.3 Gbps (NRZ) | 28.3 Gbps (NRZ) | ||
| E-Tile | GXE | 30 Gbps (NRZ), 57.8 Gbps (pulse amplitude modulation (PAM4) | 30 Gbps (NRZ), 57.8 Gbps (PAM4) | 10G/25G/100G Ethernet MAC Reed Solomon Forward Error Correction (RS-FEC) |
In Intel? Stratix? 10 devices, the various transceiver tiles are connected to the FPGA fabric using Intel? ’s Embedded Multi-die Interconnect Bridge (EMIB) technology.
Supported Features
| Feature | Description |
|---|---|
| Total transceivers | 24 dual mode channels per tile NRZ - 24 channel 1 Gbps to 30 Gbps PAM4 - 24 channel 2 Gbps to 30 Gbps PAM4 - 12 channel 30 Gbps to 57.8 Gbps |
| 10G/25G/100G Ethernet with optional 1588 capability + RS-FEC for Ethernet | Hard IP |
E-Tile Layout in Stratix 10 Device Variants
Intel? Stratix? 10 MX device configurations combine FPGAs with high-bandwidth memory.
Intel Stratix 10 TX H-Tile and E-Tile Configurations
Intel? Stratix? 10 TX FPGAs offer transceiver capability by combining H- and E-tile transceiver tiles. This section lists all possible TX FPGA configurations.
There is no package migration between Intel? Stratix? 10 GX/SX and Intel? Stratix? 10 TX device families (H-Tile and E-Tile).
Stratix 10 MX H-Tile and E-Tile Configurations
Intel? Stratix? 10 MX devices combine the programmability and flexibility of Intel? Stratix? 10 FPGAs and SoCs with 3D stacked high-bandwidth memory 2 (HBM2). The dynamic random access memory (DRAM) tile is physically connected to the FPGA using Intel? ’s Embedded Multi-die Interconnect Bridge (EMIB) technology.
There is no package migration between Intel? Stratix? 10 MX and Intel? Stratix? 10 TX device families (H-Tile and E-Tile) or Intel? Stratix? 10 GX/SX device families.
