Native Loopback Accelerator Functional Unit (AFU) User Guide


About this Document


Table 1.  Document Conventions
#Precedes a command that indicates the command is to be entered as root.
$Indicates a command is to be entered as a user.
This fontFilenames, commands, and keywords are printed in this font. Long command lines are printed in this font. Although long command lines may wrap to the next line, the return is not part of the command; do not press enter.
<variable_name>Indicates the placeholder text that appears between the angle brackets must be replaced with an appropriate value. Do not enter the angle brackets.


Table 2.  Acronyms
AFAccelerator Function

Hardware accelerator implemented in FPGA logic that accelerates or intends to accelerate an application.

AFUAccelerator Functional UnitThe supplied implementation of an accelerator, typically in HDL.
APIApplication Programming InterfaceA set of subroutine definitions, protocols, and tools for building software applications.
ASEAFU Simulation Environment

Co-simulation environment that allows you to use the same host application and AF in a simulation environment. ASE is part of the .

CCI-PCore Cache InterfaceCCI-P is the hardware-side signaling interface between the AFU and the FPGA Interface Unit (FIU).
CLCache Line64-byte cache line
DFHDevice Feature HeaderCreates a linked list of feature headers to provide an extensible way of adding features.
FIMFPGA Interface Manager (FIM)The compiled bitstream containing the FPGA Interface Unit (FIU) and other interfaces such as external SDRAM.
FIUFPGA Interface Unit (FIU)

The FIU connects the host and the AFU.

MPFMemory Properties FactoryOptimizes CCI-P traffic traffic before it reaches FIU.
MsgMessageMessage - a control notification
NLBNative LoopbackThe NLB performs reads and writes to the CCI-P link to test connectivity and throughput.
RdLine_IRead Line Invalid

Memory Read Request, with FPGA cache hint set to invalid. The line is not cached in the FPGA, but may cause FPGA cache pollution.

Note: The cache tag tracks the request status for all outstanding requests on Intel? Ultra Path Interconnect (Intel? UPI). Therefore, even though RdLine_I is marked invalid upon completion, it consumes the cache tag temporarily to track the request status over UPI. This action may result in the eviction of a cache line, resulting in cache pollution. The advantage of using RdLine_I is that it is not tracked by CPU directory; thus it will prevent snooping from CPU.
RdLine-SRead Line SharedMemory read request with FPGA cache hint set to shared. An attempt is made to keep it in the FPGA cache in a shared state.
WrLine_IWrite Line Invalid

Memory Write Request, with FPGA cache hint set to Invalid. The FIU writes the data with no intention of keeping the data in FPGA cache.

WrLine_MWrite Line Modified

Memory Write Request, with the FPGA cache hint set to Modified. The FIU writes the data and leaves it in the FPGA cache in a modified state.