Native Loopback Accelerator Functional Unit (AFU) User Guide
About this Document
Table 1. Document Conventions
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Table 2. Acronyms
Hardware accelerator implemented in FPGA logic that accelerates or intends to accelerate an application.
Accelerator Functional Unit
The supplied implementation of an accelerator, typically in HDL.
Application Programming Interface
A set of subroutine definitions, protocols, and tools for building software applications.
AFU Simulation Environment
Co-simulation environment that allows you to use the same host application and AF in a simulation environment. ASE is part of the .
Core Cache Interface
CCI-P is the hardware-side signaling interface between the AFU and the FPGA Interface Unit (FIU).
64-byte cache line
Device Feature Header
Creates a linked list of feature headers to provide an extensible way of adding features.
FPGA Interface Manager (FIM)
The compiled bitstream containing the FPGA Interface Unit (FIU) and other interfaces such as external SDRAM.
FPGA Interface Unit (FIU)
The FIU connects the host and the AFU.
Memory Properties Factory
Optimizes CCI-P traffic traffic before it reaches FIU.
Message - a control notification
The NLB performs reads and writes to the CCI-P link to test connectivity and throughput.
Read Line Invalid
Memory Read Request, with FPGA cache hint set to invalid. The line is not cached in the FPGA, but may cause FPGA cache pollution.
Note: The cache tag tracks the request status for all outstanding requests on Intel?Ultra Path Interconnect (Intel?UPI). Therefore, even though RdLine_I is marked invalid upon completion, it consumes the cache tag temporarily to track the request status over UPI. This action may result in the eviction of a cache line, resulting in cache pollution. The advantage of using RdLine_I is that it is not tracked by CPU directory; thus it will prevent snooping from CPU.
Read Line Shared
Memory read request with FPGA cache hint set to shared. An attempt is made to keep it in the FPGA cache in a shared state.
Write Line Invalid
Memory Write Request, with FPGA cache hint set to Invalid. The FIU writes the data with no intention of keeping the data in FPGA cache.
Write Line Modified
Memory Write Request, with the FPGA cache hint set to Modified. The FIU writes the data and leaves it in the FPGA cache in a modified state.